Integrated circuit with self-testing circuit

ABSTRACT

An integrated circuit ( 14 ) with an application circuit ( 1 ) to be tested and a self-testing circuit ( 5 - 13 ), which is provided for testing the application circuit ( 1 ) and generates pseudorandom test patterns, which can be transformed, by means of first logic gates ( 6, 7, 8 ) and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit ( 1 ) for testing purposes, wherein the output signals occurring through the application circuit ( 1 ) as a function of the test patterns are evaluated by means of a signature register ( 13 ), wherein, by means of second logic gates ( 10, 11, 12 ) and signals fed to said gates, those bits of the output signals of the application circuit ( 1 ) which, due to the circuit structure of application circuit ( 1 ), have undefined states, are blocked during testing.

The invention relates to an integrated circuit with an applicationcircuit to be tested and a self-testing circuit which is provided fortesting the application circuit.

In creating integrated circuits, there is a quite general desire tocheck these as regards their operation. Tests of this kind may beundertaken by external test setups. Due to the very high integrationdensity of circuits of this kind, the very high clock-pulse rates atwhich these circuits operate and the very great number of test vectorsrequired, many problems and costs arise with the external test. The highinternal clock-pulse rates of the integrated circuits are out of allproportion with the comparatively very slow input/output bonding padstages, which lead to the outside. The possibility of performing a kindof self-testing of the integrated circuit is therefore desirable. Here,a self-testing circuit is provided within the integrated circuit, whichserves to test the application circuit also provided in the integratedcircuit. The application circuit represents the circuit that is providedfor the actual intended purpose of the integrated circuit.

A further problem encountered in testing circuits of this kind is thatproblems occur with those components within the circuit that produce aso-called “X” during testing, i.e. a signal that cannot be clearlyevaluated. Signals of this kind are produced by, in particular, thosecomponents that exhibit analog or storage properties.

For example, RAMs which are provided within the application circuit mayproduce random output signals. Signals produced by a RAM of this kindand propagated through the circuit can thereby no longer beunambiguously evaluated at the circuit output during testing.

In order to circumvent these problems, the provision of specialcomponents within the circuit to permit components of this kind to bebypassed or the outputs of these components to be masked during testing,is known from the prior art. The disadvantage here is that additionalcomponents have to be provided within the circuit, resulting, on the onehand, in an increased outlay, and, on the other, in a special circuitdesign, which may occasion disadvantages.

An integrated circuit with an application circuit to be tested and aself-testing circuit, which supplies deterministic test patterns, isknown from the publication “Using BIST control for pattern generation”by Gundolf Kiefer and Hans-Joachim Wunderlich (published in Proceedings,International Test Conference 1997). This is achieved by providing, inaddition to a test-pattern generator, which is a feedback shift registersupplying pseudorandom patterns, a logic circuit which alters the outputsignal of this test-pattern generator in such a way that certaindeterministic test patterns occur. It can thereby be achieved that thecircuit can be tested with test patterns that can be predefined, and notjust with ones which are defined on a quasi-random basis by thetest-pattern generator.

It is an object of the invention to further-develop the integratedcircuit cited above to the effect that a test of the application circuitwith deterministic test patterns is possible, and that simultaneously, Xsignals occurring within the circuit during testing do not distort thetest results, whereby no additional components are to be provided withinthe application circuit.

This object is achieved according to the invention by the features asclaimed in claim 1:

An integrated circuit with an application circuit to be tested and aself-testing circuit, which is provided for testing the applicationcircuit and generates pseudorandom test patterns, which can betransformed, by means of first logic gates and signals externally fed tosaid gates, into deterministic test vectors, which are fed to theapplication circuit for testing purposes, wherein the output signalsoccurring through the application circuit as a function of the testpatterns are evaluated by means of a signature register, wherein, bymeans of second logic gates and signals externally fed to said gates,those bits of the output signals of the application circuit which, dueto the circuit structure of the application circuit, have undefinedstates, are blocked during testing.

Initially, the pseudorandom test patterns generated by the self-testingcircuit are not suitable as test vectors. Rather, they are transformedinto the desired deterministic test vectors by means of first logicgates. This is possible by means of signals externally fed to the firstgates, which are designed in such a way that, through the combination ofthe pseudorandom test patterns and the signals fed in externally, thedesired deterministic test vectors are obtained by means of the firstlogic gates.

These test patterns are fed to the application circuit, which alters thetest vectors due to the design of the application circuit. The outputsignals of the application circuit arising as a result during testingare coupled to the signature register via second logic gates. Thesignature register combines these output signals arising from multipletest cycles to form an overall final result, which represents a type ofsignature and which indicates whether the circuit is operating free fromfaults.

With this procedure, however, problems occur when components that arealmost always provided in the application circuit, which exhibit analogor storage properties, influence the output signals of the applicationcircuit during testing. So-called X signals, which deliver a “Don'tcare” result, then occur. In other words, signals marked with an X ofthis kind are random and therefore cannot be evaluated. As a result,values that likewise cannot be evaluated arise for signals of this kindin the feedback shift register. This is to be avoided.

This is achieved according to the invention in that, by means of thesecond logic gates and signals externally fed to these gates, all thebits in the output signals of the application circuit potentiallycontaining X signals of this kind are blocked. So all those bits thatare influenced by storage or analog properties of components within theapplication circuit are not passed on to the signature shift register.Only the remaining bits, which are not influenced by components of thiskind, are connected through to the signature register by means of thesecond logic gates.

It is thereby ensured that those bits which reach the signature registerduring testing can be evaluated. In turn, this means that the signatureresult present in the feedback shift register after multiple test cycleshave been run can be fully evaluated, and supplies a reliable testresult.

One important advantage of the integrated circuit with self-testingcircuit according to the invention consists in the fact that theapplication circuit does not have to be modified for the testprocedures, i.e. it can be designed in a way that is optimal for the useof the application circuit. The self-testing circuit in no wayinfluences the normal operating mode of the application circuit in itsuse.

Furthermore, the self-testing circuit according to the invention enablesa test of the application circuit to be undertaken on the chip, so thatrelatively slow output bonding pad connections do not interfere with thetesting, and the operation of the application circuit can be undertakenwith maximum clock rates of the input bonding pads.

The self-testing circuit provided on the integrated circuit is of a verysimple design and itself requires little space. The deterministic testvectors may still be amended even after the ICs have been produced.

According to one embodiment of the invention as claimed in claim 2, alinear feedback shift register provided in the self-testing circuitserves for generating the pseudorandom test patterns, which are therebyknown and can be transformed into the desired deterministic test vectorsby means of the first logic gates.

The invention will be further described with reference to an example ofan embodiment shown in the drawing, to which, however, the invention isnot limited.

The FIGURE shows, in a schematic block diagram, an integrated circuit14, which is equipped with an application circuit 1. This applicationcircuit 1 is the circuit which is designed for the use of the integratedcircuit 14.

Following production of the integrated circuit 14, there is a desire totest the application circuit 1 for satisfactory operation. To this end,a self-testing circuit, consisting of circuit elements 5 to 13 as shownin the FIGURE, is provided on integrated circuit 14.

In the integrated circuit 14 according to the invention, thisself-testing circuit is designed in such a way that it is assembledentirely outside the application circuit 1, and so that its behaviordoes not exert an influence in normal operation.

In the embodiment shown in the FIGURE, it is assumed that theapplication circuit 1 is equipped with three circuit chains 2, 3 and 4,which are shift registers. Further shift registers may also be provided.Furthermore, further circuit elements may be provided.

Within the self-testing circuit, a linear feedback shift register 5 isprovided, which supplies a pseudorandom sequence of test patterns. Sincethe shift register 5 is fed back and has only a finite length, thistest-pattern sequence is not truly random; it exhibits a pattern whichrepeats itself after specific intervals. However, this test-patternsequence has the disadvantage that it does not fully contain all testpatterns that are optimal for testing application circuit 1.

Logic gates 6, 7 and 8 are therefore provided, which alter the outputsignals of the linear feedback shift register 5 in such a way that, atthe outputs of the first logic gates 6, 7 and 8, and thereby at theinputs of application circuit 1, or its circuit chains 2, 3 or 4, testpatterns having a deterministic structure than can be predefined areproduced. This is achieved in that signals are fed to the first logicgates 6, 7 and 8 from a test setup 15 provided outside the integratedcircuit, by means of which signals the first logic gates 6, 7 and 8modify individual bits of the test patterns supplied by the linearfeedback shift register 5 in such a way that desired, deterministic testpatterns arise. The externally provided test setup is required onlyduring testing of the integrated circuit; in normal operation of theintegrated circuit, it is not present.

In the embodiment shown in the FIGURE, the test vectors are fed tocircuit chains 2, 3 and 4 within application circuit 1.

On the basis of these test patterns, circuits chains 2, 3 and 4 supplyoutput signals within application circuit 1, which output signals reacha signature register 13 via second logic gates 10, 11 and 12.

The signature register 13 is designed in such a way that it undertakes acombination of the test results over multiple test cycles, eachcontaining a test pattern, and, following the test run, supplies aso-called signature, which has to exhibit a specific, predefined valueif application circuit 1 is operating free from faults.

Here, the problem exists, however, that circuit elements may be provided(and generally are, in fact) in application circuit 1 or within itscircuit chains 2, 3 and/or 4, which circuit elements exhibit analog orstorage properties. Circuit elements of this kind do not supply anunambiguous output signal, i.e. as a function of the input signal fed tothem, they do not supply a deterministic output signal. Rather, theiroutput signal is random. It is clear that signals of this kind do notjust distort the test result, but also render specific bits within thetest result unusable.

In order, nevertheless, to be able to undertake testing of applicationcircuit 1, using the simplest possible setup, even with components ofthis kind, second logic gates 10, 11 and 12 are provided in the circuitaccording to the invention, which second logic gates are capable, as afunction of signals generated by the external test setup 15, of blockingindividual bits of the signals supplied by circuit chains 2, 3 and 4during testing, so that only those bits which are not influenced bycomponents with storage and analog properties reach the signatureregister 13 during testing.

As a result, only those bits that can be unambiguously evaluated andsupply an unambiguous result reach signature register 13. So, even ifapplication circuit 1 is equipped with components exhibiting storage oranalog properties, an unambiguous signature can be generated insignature register 13 at the end of testing, which indicates anerror-free test result.

The external test setup 15 may be a conventional test setup, which here,however, does not itself supply the test vectors, and nor does itundertake any evaluation, but supplies signals such that, within theself-testing circuit provided on the integrated circuit, the desiredtest vectors are generated from the pseudorandom sequence of numbers,and the bits that cannot be evaluated are extracted from the outputsignals of the circuit 1 under test.

Overall, by virtue of the self-testing circuit according to theinvention, testing of application circuit 1 on the chip becomes possiblewithout any restrictions arising as a result. No modification ofapplication circuit 1 is necessary, so it can be optimally designed forits actual operation. All test procedures are also possible withoutrestriction for those application circuits equipped with componentsexhibiting storage or analog properties. The desired, deterministic testvectors can still be amended, even after production of the integratedcircuit.

1. An integrated circuit (14) with an application circuit (1) to betested and a self-testing circuit (5-13), which is provided for testingthe application circuit (1) and generates pseudorandom test patterns,which can be transformed, by means of first logic gates (6, 7, 8) andsignals externally fed to said gates, into deterministic test vectors,which are fed to the application circuit (1) for testing purposes,wherein the output signals occurring through the application circuit (1)as a function of the test patterns are evaluated by means of a signatureregister (13), wherein, by means of second logic gates (10, 11, 12) andsignals externally fed to said gates, those bits of the output signalsof the application circuit (1) which, due to the circuit structure ofthe application circuit (1), have undefined states, are blocked duringtesting.
 2. An integrated circuit as claimed in claim 1, characterizedin that, within the self-testing circuit (5-13), a linear, feedbackshift register (5) is provided, which generates pseudorandom testpatterns, which are transformed into predeterminable deterministic testpatterns, by means of the first logic gates (6, 7, 8).
 3. An integratedcircuit as claimed in claim 1, characterized in that the second logicgates (10, 11, 12) block those bits of the output signals of theapplication circuit (1) that are influenced by those circuit elements ofthe application circuit (1) which have an analog behavior and/or astorage behavior.
 4. An integrated circuit as claimed in claim 1,characterized in that the signals externally fed to the first (6, 7, 8)and second (10, 11, 12) logic gates originate from a test arrangement(15) provided outside the integrated circuit.